by Aleena Parvez | Nov 14, 2025
TurboEPC redesigns the mobile packet core by offloading a subset of control plane signaling procedures to programmable dataplane switches. This improves throughput and latency by processing frequent signaling messages closer to the edge. The paper discusses challenges like user state partitioning and replication for fault tolerance, provides software and hardware prototypes using P4 switches and smartNICs, and reports up to 102% throughput increase and 98% latency reduction.
by Aleena Parvez | Nov 14, 2025
Pcube is a framework providing programming abstractions and primitives such as loops, summations, min-max, conditional tests, and state synchronization for P4-based programmable dataplanes. These simplify and reduce the complexity of writing dataplane applications like load balancers and heavy hitter detection across distributed switches. pcube preprocessor automatically expands these primitives into P4 code, enhancing developer productivity by up to 5.4x and reducing coding errors.
by Yash Sharma | Nov 14, 2025
xv6 memory management including virtual address spaces, page tables, memory allocation, and demand paging mechanisms in the xv6 teaching operating system.
by Yash Sharma | Nov 14, 2025
xv6 OS lab on process management including system call implementation, process tree operations, scheduler design, and priority-based scheduling in xv6 kernel.
by Yash Sharma | Nov 14, 2025
Practice problems on process management including process creation, scheduling algorithms, context switching, inter-process communication, and process lifecycle management.
