by Aleena Parvez | Nov 14, 2025
TurboEPC redesigns the mobile packet core by offloading a portion of signaling message processing to programmable dataplane switches, alleviating control plane bottlenecks and reducing latency. The approach partitions user state across switches, supports replication for fault tolerance, and implements series and parallel switch designs for scalability. Hardware and software prototypes demonstrate up to 102% throughput increase and 98% latency reduction.
by Aleena Parvez | Nov 14, 2025
This paper examines the performance of network functions deployed using virtualization, highlighting measurement techniques, bottlenecks, and optimization strategies for achieving high throughput in NFV platforms.
by Aleena Parvez | Nov 13, 2025
This lecture focuses on memory management techniques like virtual addressing, page tables, segmentation, paging, TLBs, and MMU operations. It discusses process isolation, address translation, and hardware-software collaboration in managing memory efficiently.
by Aleena Parvez | Nov 13, 2025
This lecture covers memory management, including virtual memory, paging, segmentation, page tables, translation lookaside buffers (TLBs), and address translation mechanisms. It explains how OS and hardware collaborate to provide isolation and efficient memory use.
by Aleena Parvez | Nov 12, 2025
This lecture explains demand paging as a virtual memory technique where only necessary pages are loaded into physical memory. It covers page tables, page faults, swap space, page replacement policies like FIFO and LRU, page fault handling, and the impact of thrashing and working sets on system performance.
