by Aleena Parvez | Nov 14, 2025
DDIOSim is an open-source, cycle-accurate simulator combining QSim and ChampSim to model Intel’s DDIO technology, which allows direct NIC-to-Last Level Cache (LLC) data transfer. The tool enables researchers to explore design, performance, and system interactions of DDIO-based network architectures, assessing cache/DRAM use, throughput, and latency for diverse workloads
by Aleena Parvez | Nov 14, 2025
This work proposes BGP Separation (BGPsep), where the forwarding and routing planes of BGP routers are decoupled, enabling more secure and robust Internet routing. The architecture allows for route validation, policy enforcement, and easier manageability of routing infrastructure, reducing attack surfaces and improving reliability.
by Aleena Parvez | Nov 14, 2025
Pyramis presents a hierarchical control-plane architecture for managing large-scale programmable networks (e.g., with many P4 switches). By partitioning device control among distributed controllers, it achieves scalability and modularity without sacrificing consistency, ensuring performance in both configuration change rate and rule installation.
by Aleena Parvez | Nov 14, 2025
AccelUPF introduces a 5G User Plane Function (UPF) that offloads both data forwarding and Packet Forwarding Control Protocol (PFCP) signaling message processing to programmable hardware like P4 switches and smartNICs. Unlike prior work, which only offloads data forwarding, AccelUPF’s full offload design demonstrates superior performance—crucial for applications with high signaling traffic (e.g., IoT)—through novel parsing, fastpath/slowpath task split, memory management, and fault tolerance for session state.
by Aleena Parvez | Nov 14, 2025
TurboEPC redesigns the mobile packet core by offloading a subset of control plane signaling procedures to programmable dataplane switches. This improves throughput and latency by processing frequent signaling messages closer to the edge. The paper discusses challenges like user state partitioning and replication for fault tolerance, provides software and hardware prototypes using P4 switches and smartNICs, and reports up to 102% throughput increase and 98% latency reduction.